snippet interface   "use it like module"
interface ${1:name} 
(
    input logic clk,
    input logic rst,
);
/*
    wire xxx;
    logic xxx;
*/

endinterface
endsnippet

snippet modport  "接口信号的不同方向"   
modport ${1:master}
(
    input                       ${2:clk},
    output                      ${2:clk},
);
endsnippet

snippet interface_axis_stream 
interface if_axi_stream #
(
    parameter int DATA_WIDTH = 32
)
();

logic                   tvalid;
logic                   tready;
logic [DATA_WIDTH-1:0]  tdata;
logic                   tlast;
logic [23:00]           tuser;
logic [31:00]           tlen;

modport master 
(
    output tdata,
    output tvalid,
    input  tready,
    output tlast,
    output tuser,
    output tlen
);

modport slave 
(
    input  tdata,
    input  tvalid,
    output tready,
    input  tlast,
    input  tuser,
    input  tlen
);

endinterface
endsnippet

snippet interface_axi4_full
interface if_axi4_full #
(
    parameter int DATA_WIDTH = 32
)
();
    logic     [3:0]           awid;
    logic     [31:0]          awaddr;
    logic     [7:0]           awlen;	// 一次突发事务中传输的单位个数. 实际传输的长度 = awlen + 1 
    logic     [2:0]           awsize;	// 每个单位的宽度. 例如32bit传输时，AWSIZE = 3'b010
    logic     [1:0]           awburst;
    logic     [0:0]           awlock;
    logic     [3:0]           awcache;
    logic     [2:0]           awprot;
    logic     [3:0]           awqos;
    logic                     awvalid;
    logic                     awready;

    logic     [511:0]         wdata;
    logic     [63:0]          wstrb;
    logic                     wlast;
    logic                     wvalid;
    logic                     wready;

    logic                     bready;
    logic      [3:0]          bid;
    logic      [1:0]          bresp;
    logic                     bvalid;

    logic     [3:0]           arid;
    logic     [31:0]          araddr;
    logic     [7:0]           arlen;
    logic     [2:0]           arsize;
    logic     [1:0]           arburst;
    logic     [0:0]           arlock;
    logic     [3:0]           arcache;
    logic     [2:0]           arprot;
    logic     [3:0]           arqos;
    logic                     arvalid;
    logic                     arready;

    logic                     rready;
    logic      [3:0]          rid;
    logic      [511:0]        rdata;
    logic      [1:0]          rresp;
    logic                     rlast;
    logic                     rvalid;

// 定义一个 modport master，用于数据发送方
modport master 
(
  output    awid,
  output    awaddr,
  output    awlen,
  output    awsize,
  output    awburst,
  output    awlock,
  output    awcache,
  output    awprot,
  output    awqos,
  output    awvalid,
  input     awready,

  output    wdata,
  output    wstrb,
  output    wlast,
  output    wvalid,
  input     wready,

  output    bready,
  input     bid,
  input     bresp,
  input     bvalid,

  output    arid,
  output    araddr,
  output    arlen,
  output    arsize,
  output    arburst,
  output    arlock,
  output    arcache,
  output    arprot,
  output    arqos,
  output    arvalid,
  input     arready,

  output    rready,
  input     rid,
  input     rdata,
  input     rresp,
  input     rlast,
  input     rvalid
);
endinterface
endsnippet

snippet interface_ax4lite

endsnippet
